The present invention relates to a continuous-time delta-sigma Analog to Digital Converter (ADC), and more particularly, to a continuous-time delta-sigma ADC with a compact structure.
The delta-sigma ADC, also referred as the Δ/Σ ADC, has a major advantage of shaping the quantization noise spectrum for efficiently removing the noise from the output. More specifically, the delta-sigma ADC can move the noise from low frequencies into high frequencies so that the noise of the output can be filtered out by a low-pass filter. Since the continuous-time delta-sigma ADC is able to operate at a higher sampling frequency than the discrete-time delta-sigma ADC, the continuous-time delta-sigma ADC is more applicable in wireless communication receivers.
Please refer to FIG. 1. FIG. 1 is a diagram illustrating a conventional continuous-time delta-sigma ADC 100. The continuous-time delta-sigma ADC 100 comprises a loop filter 110, a summing circuit 120, a quantizer 130, and a current Digital to Analog Converter (DAC) 140. The loop filter 110 noise-shapes an analog input signal SAIN, and then accordingly outputs a positive loop voltage VL+ and a negative loop voltage VL−. The summing circuit 120 comprises a positive input resistor RI+, a negative input resistor RI−, a positive feedback resistor RF+, a negative feedback resistor RF−, and a fully differential amplifier 121. The resistors RI+, RI−, RF+, and RF− all have the same resistance R. The summing circuit 120 generates a positive summing voltage VS+ and a negative summing voltage VS− according to a positive feedback current IFB+, a negative feedback current IFB−, and the loop voltages VL+ and VL−. The quantizer 130 outputs a digital output signal SDOUT according the difference between the summing voltages VS+ and VS−. The current DAC 140 drains/sources the positive feedback current IFB+ from/to the summing circuit 120, and sources/drains the negative feedback current IFB− to/from the summing circuit 120 according to the value of the digital output signal SDOUT. For example, when the value of the digital output signal SDOUT is larger than zero, the current DAC 140 sources the positive feedback current IFB+ to the summing circuit 120 and drains the negative feedback current IFB− from the summing circuit 120; when the value of the digital output signal SDOUT is smaller than zero, the current DAC converter 140 drains the positive feedback current IFB+ from the summing circuit 120 and sources the negative feedback current IFB− to the summing circuit 120. The magnitudes of the feedback currents IFB+ and IFB− are both (NDOUT×IDAC), wherein IDAC is the magnitude of the Least Significant Bit (LSB) current of the current DAC 140, and NDOUT is a value represented by the digital output signal SDOUT. For example, when the value NDOUT represented by the digital output signal SDOUT is (+3), the current DAC 140 drains the positive feedback current IFB+ from the summing circuit 120 and sources the negative feedback current IFB− to the summing circuit 120 with the magnitude 3×IDAC; when the value NDOUT represented by the digital output signal SDOUT is (−2), the current DAC 140 sources the positive feedback current IFB+ to the summing circuit 120 and drains the negative feedback current IFB− from the summing circuit 120 with the magnitude 2×IDAC. The difference between the summing voltages VS+ and VS− can be represented by the following formula:(VS+−VS−)=(VL+−VL−)−2×NDOUT×IDAC×R  (1).
Since the structure of the conventional continuous-time delta-sigma ADC is complicated, the layout area is wasted and the loop delay is increased, causing a higher cost and worse system stability.